Huawei can't make smaller transistors. So it's redefining what 'scaling' means.
Barred from EUV lithography, Huawei unveiled a 'Tau' scaling law and a LogicFolding architecture that target 1.4nm-equivalent performance by 2031 — a bet on optimizing time and wiring instead of shrinking the transistor. Sovereignty engineering, turning a constraint into a thesis.
May 25, 20263 min read
