Huawei can't make smaller transistors. So it's redefining what 'scaling' means.
Barred from EUV lithography, Huawei unveiled a 'Tau' scaling law and a LogicFolding architecture that target 1.4nm-equivalent performance by 2031 — a bet on optimizing time and wiring instead of shrinking the transistor. Sovereignty engineering, turning a constraint into a thesis.
Huawei can't buy the machines that make smaller transistors. So on Monday, at the IEEE ISCAS conference in Shanghai, it proposed changing what "smaller" means. He Tingbo — chair of Huawei's Scientist Committee and head of its semiconductor business — unveiled the Tau (τ) Scaling Law, a design principle that swaps the industry's decades-long obsession with shrinking transistors for shrinking time: the delay it takes signals and data to move through a chip and the system around it. Paired with a new architecture called LogicFolding, Huawei says the approach can deliver chips with density and performance equivalent to a 1.4-nanometer process by 2031 — without the advanced lithography U.S. sanctions have put out of reach.
What was actually announced
Two things, and the distinction matters. The Tau Scaling Law is the framing: instead of measuring progress by feature size (the "nanometer" race gated by EUV lithography), measure it by how fast data moves end to end, and optimize the whole stack — transistor, interconnect, packaging, system — against that clock. LogicFolding is the concrete technology: it folds and shortens the wiring inside a chip to cut resistive and capacitive load, raising effective transistor density and speed. Huawei says LogicFolding debuts in the Kirin chips shipping this fall, and that it has already used the broader method to design and mass-produce 381 chips over six years.
The honest caveat, which Huawei did not hide and we won't either: there is no independent performance data behind the 2031 target. "1.4nm-equivalent" is a claim of comparable performance, not a claim that Huawei will fabricate at 1.4nm. It's a roadmap, not a benchmark.
Our read
This is sovereignty engineering, and it's a genuinely clever reframe. When Washington cut China off from EUV machines, it didn't just slow Huawei down — it removed the one axis (geometric shrink) on which the entire industry had agreed to compete. Huawei's response is to refuse the game and propose a different scoreboard: if you can't win on size, win on time, architecture, and packaging, where the tools you can get still have headroom. Branding it a "scaling law" — echoing Moore — is no accident. Part of this is real engineering; part of it is morale and narrative, planting a flag that says China has its own trajectory, on its own terms.
The strategy isn't crazy, either. The mainstream industry already concedes that pure transistor shrink is running out of road, which is why everyone is pouring effort into advanced packaging, chiplets, and interconnect — the same territory Tau stakes out. Huawei is making a constraint into a thesis. The question is how far architecture and packaging can carry you before physics and yield costs bite, and on that, a 2031 date with no third-party numbers is a promise, not proof. Folding wiring buys density and speed, but it adds manufacturing complexity, and "equivalent to 1.4nm" is the kind of phrase that survives precisely because it's hard to falsify.
Zoom out and a pattern snaps into focus: three blocs, three sovereignty bets, all announced within days. The U.S. is subsidizing the next manufacturing base outright — see IBM's Anderon quantum foundry. Europe is consolidating its labs and chasing "sovereign" alternatives, the logic behind its deeptech push. And China, denied the tools, is trying to change the rules of the contest itself. Export controls were meant to freeze China a few nodes behind. What they may actually be doing is forcing it down a different research road — one where the metric isn't the nanometer, and where, if it works, the rest of the industry eventually has to follow.
The first real datapoint isn't the 2031 slide. It's this fall's Kirin, the first silicon to carry LogicFolding. If the performance shows up, "Tau" stops being a keynote and starts being a roadmap everyone has to take seriously. If it doesn't, it's a very well-branded way of saying not yet.
